EPFL/STI/IEL/LSM
Expert in chip design, intelligent detector, VLSI design, high-level specification and synthesis, sensors development
Yusuf Leblebici
EPFL
ULP-Logic
ULPLogic: Sub-Threshold Source-Coupled Logic (ST-SCL) Circuits for Ultra Low Power Applications

EPFL/STI/IEL/LSM
Expert in chip design, intelligent detector, VLSI design, high-level specification and synthesis, sensors development
Yusuf Leblebici
EPFL

Project Description

The demand for implementing ultra-low power digital systems in many modern applications such as mobile systems, sensor networks, and implanted biomedical systems, has made the design of logic circuits in sub-threshold regime a very important challenge. In sub-threshold MOS devices, current density is very low and the ratio of the transconductance to bias current of the device (gm/ID) is maximum. Meanwhile, the exponential relationship between drain current and gate voltage can make them very suitable for implementing widely adjustable circuits. CMOS logic circuits utilizing subthreshold transistors can operate with very low power consumption. In this type of circuits, the power dissipation is mainly due to the dynamic (switching) power consumption and is quadratically dependent to the supply voltage. Hence, reducing the supply voltage will result in reduction of power dissipation as well as the output logic swing. Supply voltage reduction, on the other hand, increases the delay in each gate which means the power dissipation, logic swing, and speed of operation are tightly related to each other. Meanwhile, the exponential relationship between power dissipation and supply voltage in sub-threshold regime makes the accurate control of power consumption difficult. To implement very low power digital systems, it is necessary to minimize the energy dissipation at the system level in addition to the gate level to achieve the desired performance.  

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Notable publications

Subthreshold Source-Coupled Logic
A. Tajalli and Y. Leblebici


A 9 pW/Hz Adjustable Clock Generator with 3-Decade Tuning Range for Dynamic Power Management in Subthreshold SCL Systems
A. Tajalli and Y. Leblebici
Proceedings of the European Solid-State Circuits Conference (ESSCIRC), Seville, Spain, September 13-17, 2010.

Subthreshold Current-Mode Delta-Sigma Quantizer with 3-Decade Scalable Sampling Rate and pico-Ampere Range Resolution
A. Tajalli and Y. Leblebici
Proceedings of the European Solid-State Circuits Conference (ESSCIRC), Seville, Spain, September 13-17, 2010

A Widely-Tunable and Ultra-Low-Power MOSFET-C Filter Operating in Subthreshold
A. Tajalli, Y. Leblebici
Custom Integrated Circuits Conference (CICC), pages 593-596. IEEE, 2009


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